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W9812G2GB 1m 4 banks 32bits sdram table of contents- 1. genera l des cription ............................................................................................................ .. 3 2. features ....................................................................................................................... ............... 3 3. available par t numb er .......................................................................................................... 3 4. ball confi g uration ............................................................................................................. .... 4 5. pin descri ption ................................................................................................................ ......... 5 6. block diagram .................................................................................................................. ......... 6 7. functiona l desc ription ........................................................................................................ 7 7.1. power up and in itializ ation ................................................................................................. 7 7.2. programmi ng m ode regi st er .............................................................................................. 7 7.3. bank ac tivate command .................................................................................................... 7 7.4. read and wri te a ccess modes .......................................................................................... 7 7.5. burst read command ........................................................................................................ 8 7.6. burs t write command ......................................................................................................... 8 7.7. read interrupt ed by a read ............................................................................................... 8 7.8. read interrupt ed by a writ e ................................................................................................ 8 7.9. write interrupted by a writ e ................................................................................................ 8 7.10. write interrupted by a read ................................................................................................ 8 7.11. burs t stop command .......................................................................................................... 9 7.12. addressing s equence of sequentia l mode ......................................................................... 9 7.13. addressing s equence of interleave mode .......................................................................... 9 7.14. auto-prec h ar g e c o m m a n d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.15. precharge command ........................................................................................................ 10 7.16. self refres h comm and ..................................................................................................... 10 7.17. power down mode ............................................................................................................ 11 7.18. no operatio n command ................................................................................................... 11 7.19. des e lec t command .......................................................................................................... 11 7.20. cloc k sus pend mode ........................................................................................................ 11 8. operatio n mode ................................................................................................................. ..... 12 9. electrica l cha ra cteristics ............................................................................................. 13 9.1. abs o lute maximu m ratings .............................................................................................. 13 9.2. rec o mmended dc operat ing condit ions ........................................................................ 13 9.3. capac i tance .................................................................................................................... .. 13 9.4. dc charac teri s t ics ............................................................................................................ 1 4 pub lica tio n relea s e da te: aug . 13 ,2 007 - 1 - revi si on a0 7
W9812G2GB 9.5. ac characteristics and operating co ndi tion .................................................................... 15 10. timing wa v e forms ............................................................................................................... ... 17 10.1. comm and input timing ..................................................................................................... 17 10.2. read ti ming .................................................................................................................... .. 18 10.3. cont rol timing of input/output data ................................................................................. 19 10.4. mode regi st er set cycle .................................................................................................. 20 11. operating timi ng example .................................................................................................. 21 11.1. interleaved bank read (burs t length = 4, cas latenc y = 3) .......................................... 21 11.2. interleaved bank read (burs t length = 4, cas latenc y = 3, auto-prec h arge) ............... 22 11.3. interleaved bank read (burs t length = 8, cas latenc y = 3) .......................................... 23 11.4. interleaved bank read (burs t length = 8, cas latenc y = 3, auto-prec h arge) ............... 24 11.5. interleaved bank write (b urs t lengt h = 8) ....................................................................... 25 11.6. interleaved bank write (b urs t length = 8, auto -precharge) ............................................ 26 11.7. page mode read (burst lengt h = 4, ca s lat ency = 3) ................................................... 27 11.8. page mode read / write (b urst length = 8, cas latency = 3) ....................................... 28 11.9. auto-precharge read (burst length = 4, cas latency = 3) ............................................ 29 11.10. auto-precharge write (burst lengt h = 4) .......................................................................... 30 11.11. auto refres h cyc l e ........................................................................................................... 31 11.12. self refres h cyc l e ............................................................................................................ 3 2 11.13. burst read and single wri te (burst length = 4, cas latency = 3) ................................. 33 11.14. power down mode ............................................................................................................ 34 11.15. auto-precharge timi ng (read cy cle) ............................................................................... 35 11.16. auto-prec h arge timing (write cy c l e) ............................................................................... 36 11.17. timing chart of read to write cycl e ................................................................................ 37 11.18. timing chart of write to read cyc l e ................................................................................ 37 11.19. timing chart of burs t stop cy c l e (burs t st op comma nd) ............................................... 38 11.20. timing chart of burs t stop cy c l e (prec h arge command) ................................................ 38 11.21. cke/dqm input timing (write cyc l e) .............................................................................. 39 11.22. cke/dqm input timi ng (read cy cle) .............................................................................. 40 12. package specific ation ......................................................................................................... 4 1 12.1. tfbga 90 balls pi tch=0.8mm .......................................................................................... 41 13. revision hi stor y ............................................................................................................... ...... 42 pub lica tio n relea s e da te: aug . 13 ,2 007 - 2 - revi si on a0 7
W9812G2GB 1. general descrip t ion w98 12g 2gb is a high -spe ed syn c h r on o u s dyna mic rando m acce ss memo ry (s dram ) , org a n ize d as 1,048,57 6 wo rd s 4 ban ks 32 bits. usi ng pip e lin ed archite c tu re and 0.1 1 m pro c e ss t e ch nolo g y, w98 12g 2gb delivers a data ban dwi d th of up to 166m hz word s pe r se cond (-6 ) . for differen t appli c ation, w98 12g 2gb is sorted int o two spe ed gra d e s : -6/-6i and -75. th e ?6 is com p liant to th e 166m hz/cl 3 spe c ificatio n (the -6i gra d e whi c h is g uarantee d to supp ort -4 0 c ~ 85 c). the -75 i s com p liant to the 133 mh z/cl3 sp ecifi c ati on. accesse s to the sdram are burst oriente d . con s e c utive memory locatio n in one page can b e acce ssed at a burst length of 1, 2, 4, 8 or full page when a ban k and ro w is sele cted by a n active comm and. column ad dre s ses a r e aut omatically gener ated by the sdram intern al cou n ter in burst ope ration. rando m colu mn rea d is a l so po ssible by providing its address a t each cl ock cycle. th e multiple ba nk nature e nabl es inte rleavin g amon g internal ban ks to hide the p r e c harging time. by having a programma ble mode r egiste r , the system ca n cha nge bu rst length, late ncy cycle , interle a ve or seq uential bu rst to maximi ze its per fo rman ce. w98 12g2 g b is id eal for m a in memo ry in high pe rform ance appli c ati ons. 2. feat ure s ? 3.3v 0.3v powe r suppl y ? up to 166 m h z clo ck f r e quen cy ? 1,048,57 6 word s 4 ba nks 32 bit s organi zation ? self refre s h mode ? cas laten cy: 2 and 3 ? burst le ngth: 1, 2, 4, 8 and full page ? burst read, single writes mode ? byte data controlled by dqm ? auto-p re cha r ge and cont rolled pre c h a rge ? 4k refre s h cycles / 64 ms ? interface: lvttl ? packag ed in tfbga 90 ball ? w98 12g 2gb is usin g lead free mate rial s with ro hs complia nt 3. availabl e part number part n u mb er sp ee d maximum self refr esh c urr ent operating temperatu r e w98 12g 2gb - 6 1 6 6 m hz/cl 3 2 m a 0 c ~ 7 0 c w98 12g 2gb - 6 i 1 6 6 m hz/cl 3 2 m a -40 c ~ 8 5 c w98 12g 2gb - 7 5 1 3 3 m hz/cl3 2 m a 0 c ~ 7 0 c pub lica tio n relea s e da te:aug . 13 ,2 007 - 3 - revi si on a0 7
W9812G2GB 4. ball co nfiguration cke a8 a6 dq23 a4 clk a9 a7 a5 we# cas# cs# bs0 a10 a1 a3 dqm0 ras# bs1 a0 a2 1 26 5 7 9 8 4 3 c b a p n g d e m h l f k r j vdd vdd vdd vddq vddq vddq vddq vddq vdd vddq vddq vddq vddq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vddq nc nc a11 nc nc dqm2 dq21 dq19 dq20 dq22 dq18 dq17 dq16 dq7 dq6 dq5 dq1 dq3 dq4 dq0 dq2 vss vss vss vss dqm3 dqm1 dq26 dq24 dq28 dq27 dq25 dq29 dq30 dq31 dq15 dq13 dq11 dq12 dq14 dq10 dq9 dq8 nc nc top view pub lica tio n relea s e da te: aug . 13 ,2 007 - 4 - revi si on a0 7
W9812G2GB 5. pin des c ription ball location pin n a me function descri ptio n g1~g3,g7~g9 , f2,f 3,h1,h2,j3,h 9 a0 ? a11 address multipl e xed pin s for ro w a nd c o lumn addr ess . ro w addr ess: a0 ? a 11. col u mn ad dress: a0 ? a7. a10 is sample d dur in g a prech a rge command to d e termine if a ll banks ar e to be prech a rge d o r bank sel e cted b y bs0, bs1. j7,h8 bs0, bs1 bank select select ba nk to activate dur ing ro w ad dress lat c h time, or bank to rea d / w rite durin g ad dr ess latch time. a1,a2,a8,a9,b1,b9, c2,c3,c7,c 8, d2,d3, d7,d8,e2,e8,l 2 ,l8, m2,m3,m7,m8,n2,n3 ,n7,n8,p1,p9, r 1,r2, r8,r9 dq0 ? dq3 1 data input/ output multipl e xed pin s for data outp u t and in put. j8 cs chip s e lect disab le or e n a b le the comm a nd dec oder. w hen comm and deco der is dis a bled, n e w com m and is i gnor e d and previo us op era t ion conti nues. j9 ras ro w ad dress strobe comman d in pu t. w hen sampl ed at the risin g edge of the clock ra s , cas an d we defin e the op er ation to be execute d . k7 ca s colum n addr e ss strobe referred to ras k8 we w r ite enabl e referred to ras f 2 ,f 8 , k 1 , k 9 d q m 0 ~ 3 input/outp u t m a s k t he output buffer is plac ed at hi-z ( w ith l a ten c y of 2) w h en dqm is sampl ed hi gh in re ad c y cle. in w r it e c y cl e, sampli ng dqm high w i ll bl ock t he w r ite op era t ion w i th zer o latenc y. j 1 c l k c l o c k i n p u t s s y stem clock u s ed to sampl e i nputs on th e rising e dge of clock. j 2 c k e c l o c k e n a b l e cke controls t he clock activ a tion an d de acti vation. w hen cke is lo w , po w e r do w n m o d e , suspen d mo de, or self refresh mo de i s entered. a7,f 9,l7,r7 vdd po w e r (+ 3.3v) po w e r for in put buffers and lo gic circuit ins i d e dram. a3,f1,l3,r3 vss ground ground for in p u t buffers and l ogic circu i t insi de dram. b2,b7,c9,d9,e 1 ,l1, m9,n9,p2, vddq po w e r (+3.3v) for i/o buffer separ ated p o w e r from vdd, to improve dq noise immunit y . b8,b3,c1,d1,e 9 ,l9, m1,n1,p8, vssq ground for i/o buffer separ ated gro und from vss, to improve dq noise immunit y . e3,e7,h3,h7, h9, k2,k3 nc no con necti on no con nectio n pub lica tio n relea s e da te:aug . 13 ,2 007 - 5 - revi si on a0 7
W9812G2GB 6. block di agram dq 0 dq3 1 dq mn cl k ck e cs ra s ca s we a1 0 a0 a9 a1 1 bs0 bs1 . cl ock bu f f e r co mm an d de co de r a ddres s bu f f e r refres h co unte r col u mn counter cont rol signal g e nera t o r mo d e register an d em rs co l u m n de co de r se n se a m p l i f i e r c e ll a rray ba nk #2 co l u mn de co de r se n se a m p l i f i e r cell a rray ba nk #0 co l u mn de co de r se n se a m p l i f i e r cell a rray ba nk #3 data co ntrol circ uit dq bu f f e r co l u mn de co de r se n se a m p l i f i e r cell a rray ba nk #1 not e : t h e cel l a rray co nf ig ura t i o n i s 40 96 * 2 56 * 32 dm n ro w de code r ro w de code r ro w de code r ro w de code r pub lica tio n relea s e da te: aug . 13 ,2 007 - 6 - revi si on a0 7
W9812G2GB 7. functional de scription 7.1. po w e r up and initiali zation the defa u lt power u p st ate of the mode regi ste r is u n spe c ified. the foll owin g po we r up an d initializatio n seque nce nee d to be followed to guara n tee the device being pre c o n d itioned to ea ch user specific needs. du ring p o wer up, all v dd and v ddq pins mu st be ramp up simu ltaneou sly to the spe c ifie d voltage whe n the inp u t signal s are held in the ?nop? st ate. the po wer u p voltage must not exceed v dd +0. 3 v on any of the input pin s or v dd supplie s. after power up, an initial pau se of 200 s is requi re d followe d by a precha rge of all ban ks u s in g the p r ech a rge com m and. to pre v ent data con t ention on the dq bu s duri ng po we r up, it is re qui red that the dqm and cke pins be h e ld high d u rin g th e initial pa use perio d . once all ban ks h a ve bee n precha rge d , the mode re giste r set co mmand mu st be issu ed to initialize the mode re giste r . an additional eig h t auto refre s h cycle s (cb r ) are al so re quired befo r e or after pro g ra mming the mode re giste r to ensu r e prope r sub s eq uent op eration. 7.2. programming mode register after initial powe r up, the mode regi ster set comm and mu st be issued for p r ope r device ope ration. all banks mu st be in a p r ech a rged sta t e and cke must be high at least on e cycle before the mode regi ste r set comm and ca n be issue d . the mode regi ste r set comm and i s activated by the low sign als of ra , s ca s , cs and we at the positive ed ge of the clock. the ad dre s s input data duri ng this cy cle d e fine s th e paramete r s to be set a s sho w n i n the mode regi st er op eration table. a new co mman d may be i ssued follo win g the mod e re giste r set co mmand on ce a delay e q u a l to t rsc has el ap sed. please refe r to the next page for mo d e regi ste r set cycle a nd op eratio n table. 7.3. bank acti v a te co m m a nd the ban k activate comma nd mu st be a pplied before any rea d o r write o peration can be execute d . the ope ratio n is similar to ra s activate in edo dra m. the delay from when the bank acti vate comm and i s applie d to wh en the first re ad or write op eratio n can b egin m u st n o t be le ss th an the ras to cas delay time (t rcd ). once a ban k has b een a c ti vated it must be precharge d before anot her ban k activate com m and can be issue d to th e same ba nk. the minimum time interval betwee n succe ssive bank activate comma nd s to the same ban k is det ermined by the ras cycle time of the device (t rc ). the minimu m time interval betwe en interleaved ban k activate com m and s (ban k a to bank b and vice versa) is the bank to bank delay time (t rrd ). the ma ximum time that each ba n k can be held active is s p ec ifie d as t ras (max ). 7.4. re ad and write acc e ss mode s after a bank has be en acti vated, a read or write cy cle can be follo wed. this is accom p lished b y setting ras high and ca low at the clo ck ri sin g edg e after minimum of t s rc d delay. we pin voltage level define s whet her the acce ss cy cle i s a read o peratio n ( we high), or a write ope rat i on ( we low). the add re ss in put s dete r mine t he sta r ting co lumn ad dre ss. rea d ing or writing to a differe nt ro w wit h in an activat ed ba nk re qu ire s the b a n k be p r e c ha rg ed an d a new ban k activate comm and be issu e d . when mo re than one b ank i s activated, interleav ed ban k rea d o r writ e op eratio ns are po ssi ble. by usin g th e prog ramm e d bu rst l engt h an d alte rn ating the acce ss a nd pre c h a rg e op eratio ns b e tween multipl e ban ks, seaml e ss data a ccess ope ratio n amon g pub lica tio n relea s e da te:aug . 13 ,2 007 - 7 - revi si on a0 7
W9812G2GB many differen t pages can b e reali z ed. read or write comm and s can also be issue d to the same ban k or bet wee n a c tive ban ks o n every clo c k cycle. 7.5. burs t re ad command the bu rst read comm an d is initiate d by applying logic l o w l e vel to cs and ca s while holding ras and we high a t the rising ed ge of the clock. the add re ss input s determine the start i ng col u mn add re ss fo r the bu rst. the mode regi ster sets type of burst (seq uential o r interle a ve) a nd the burst length (1, 2, 4, 8 and full p age ) durin g the mode reg i ster set up cycle. table 2 and 3 in the next page explain the a ddress sequ e n ce of in te rle a ve mode a n d seq uential mode. 7.6. burs t writ e comman d the burst write comm an d is initiated by applying logic low le vel to cs , cas an d we while holdin g ras high at the rising edge of t he clock. the ad dre s s inputs determi ne the starting col u mn add re ss. data for the first burst write cycle mu st be applie d on th e dq pin s on the same cl ock cycl e that the write comma nd is issu ed. the remai n ing d a ta inputs mu st be sup p lied on ea ch sub s eque nt risi ng cl ock e dge until the burst length i s com p lete d. data suppli e d to the dq pins afte r burst finishe s will be ignored. 7.7. re ad interrupted by a re ad a burst read may be interrupte d by another read co mman d . wh en the previo us bu rst is interrupted, the remai n ing addresse s a r e overrid den by the new read ad dress with the full b u rst length. t he data from the first read com m and contin ues to app ea r on the outp u ts until the cas laten cy from the interrupting read comma n d the is sati sfied. 7.8. re ad interrupted by a write to interrupt a burst read with a write comm and, dqm m a y b e nee ded to place the dqs (output drivers) in a high impe dan ce state to avoid dat a con t ention on the dq bu s. if a rea d com m and wil l issue d a ta on the first a nd se con d cl ocks cy cle s of th e write op era t ion, dqm i s need ed to in su re th e dq s a r e tri - stated. after that point th e write co m m and will h a v e cont rol of the dq bu s and dqm maskin g is no longe r nee de d. 7.9. write interrupted by a write a burst write may be interrupted befo r e com p letion of the burst by anothe r write comman d . whe n the previo us burst is interru p te d, the re main ing ad dresse s a r e ove rri d den by th e n e w a d d r e ss and d a ta will be written into the device until the p r ogramme d b u rst length is satisfie d. 7.10. write interrupted by a re ad a read co mmand will interrupt a burst write op erat io n on the same cl ock cycle that the rea d comm and i s activated. th e dqs mu st be in the hi gh impeda nce state at least one cycle b e fore the new re ad d a t a appe ars o n the outp u ts to avoid d a ta co ntentio n. whe n the rea d com m and i s activated, any residual dat a from t he burst write cycl e will be ignored. pub lica tio n relea s e da te: aug . 13 ,2 007 - 8 - revi si on a0 7
W9812G2GB 7.11. burs t stop command a burst stop comm and m a y be used to terminate the existing burst operation bu t leave the bank ope n for future re ad or write comm and s t o the same page of the active ba nk, i f the burst le ngth is full page. use of the burst stop comma nd durin g othe r burst length ope ration s is illegal. the b u rst stop comm and i s defined by h a ving ra s and ca s high with cs and we low at th e ri sing edg e of the clo ck. th e data dq s g o to a high impeda nce stat e after a dela y which i s eq ual to the cas latency in a burst rea d cycle inte rrupted by burst stop. 7.12. addressin g sequence of sequential mode a colum n a c ce ss i s perfo rmed by in creasi ng the a ddr ess fro m the colum n a ddress whi c h is in put to the device. t he distu r b a d d re ss is varie d by the burst length as shown in tabl e 2. table 2 add r ess sequ enc e of sequen t ial mode d a t a a c c e ss ad d r e s s bur st len g t h data 0 n bl = 2 (di s turb add re ss i s a0) data 1 n + 1 no ad dress carry from a0 t o a1 data 2 n + 2 bl = 4 (di s turb add re sses are a0 an d a1) data 3 n + 3 no ad dress carry from a1 t o a2 data 4 n + 4 data 5 n + 5 bl = 8 (di s turb add re sses are a0, a1 an d a2) data 6 n + 6 no ad dress carry from a2 t o a3 data 7 n + 7 7.13. addre ssin g sequenc e of interle ave mod e a column a ccess is sta r ted in the input colu mn ad dre ss a nd is p e rf orme d by inverting the ad dre s s bit in the seq uen ce sho w n in table 3. table 3 add r ess sequ enc e of interle a v e mode d a t a a c c e s s ad d r e s s bur s t len g t h data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 2 data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 4 data 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a 0 bl = 8 data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a8 a7 a6 a5 a4 a3 a2 a1 a0 pub lica tio n relea s e da te:aug . 13 ,2 007 - 9 - revi si on a0 7
W9812G2GB 7.14. auto-prech arge command if a10 is set to high when t he re ad or write comm and is i s sued , then the auto-p r e c ha rg e functio n is entered. duri ng auto-prechar ge, a read command will execute as nor m a l with the exception that the active ban k will begin to pre c h a rg e au tomatically b e fore all bu rst read cycle s have been complete d. reg a rdle ss o f burst length , it will begin a certai n nu mber of clo cks prio r to the end of the sche dule d burst cycl e. the num ber of clocks is det ermin ed by cas latency. a read or write comm and with aut o-p r e c ha rg e c an not be interrupted b e fore the en tire burst ope ration is complete d. therefo r e, use of a read, write or pre c ha rge comma n d is prohi bite d durin g a rea d or write cycle with a u t o-precha rge. once t he prech a rge ope ration has st a r ted, the ban k can not be rea c tivate d until the prech a rge time (t rp ) has be en sati sfied. issue of auto-pre ch arg e co mmand i s illegal if the b u rst is set to full pag e len g th. if a 10 is high when a write co mman d is issu ed, the writ e with auto-p re cha r g e functi on is initiate d . the sdra m automatically enters the pre c h a rg e ope ration two clo c ks d e lay from th e la st bu rst write cycl e. this delay i s refe rre d to as write t wr . t h e ba nk unde rg oing a u to-p re cha r g e ca n not be rea c tivated u n til t wr a nd t rp are satisfie d. this i s refe rre d to a s t dal , data-in to active delay (t da l = t wr + t rp ). when usin g the auto-p re cha r g e comm and, the interval betwe en the bank activate comma nd and the begi nni ng of the intern al pre c harge ope rati on must sat i sf y t ras (m i n ) . 7.15. prech arg e command the pre c ha rge comm an d is used to prech a rge or clo s e a bank that has been activa ted. the precha rge comman d is e n tere d wh en cs , ra s and we are low an d ca s is h i gh at the risi ng edge of the clock. the precha rg e com m and ca n be used to precharge each bank sepa ratel y or all ban ks sim u ltaneo usly. th ree ad dress bi ts, a10, bs0, and bs1, are used to d e fine which ba n k (s) i s to be precha rge d wh en the comman d is i s sue d . after the pre c ha rg e comm and i s i s sued, the prech a rge d ban k mu st be rea c tivated b e fore a ne w read o r wr ite acce ss ca n b e executed. t he del ay bet wee n the precha rge comman d an d the activate comm and m u st be g r e a te r than o r eq u a l to the pre c harge time (t rp ). 7.16. self ref r e s h comman d the self ref r e s h comma nd is d e fined by having cs , ra s , ca s and cke held lo w wit h we high at the rising edg e of th e clock. all banks mu st be idle prior to issuing the se lf refresh co mmand. once the co mmand i s re giste r ed, cke must b e h e ld lo w to ke ep the device in self refre s h mo de . whe n the sdram ha s e n tere d self ref r e s h mo de all of the extern al co ntrol si g nals, ex cept cke, are disa bled. the clock is inte rnally disa bled during self refre s h ope r at ion to save p o we r. the de vice will exit self refresh ope ratio n after cke i s retu rn ed hi gh. a minimu m delay time is re quired whe n the device exits self refresh ope r ation an d before t he next comman d can be issu ed. this dela y is equal to the t ac c y c l e time plus the self refresh exit time. if, during no rmal operation , auto refresh cycl es are issued in burst s (as o ppo sed to bei ng evenly distri buted ), a burst of 4,09 6 auto ref r esh cycle s sho u ld b e complete d just prio r to ente r ing a n d just after exiti ng the self re fresh mod e . the pe ri o d b e twee n the a u to refresh comman d an d the next comm and i s spe c ified by t rc . pub lica tio n relea s e da te: aug . 13 ,2 007 - 10 - revi si on a0 7
W9812G2GB 7.17. po w e r do w n mode the power down mo de is initiated by holdin g cke lo w. all of th e receiver ci rcuits ex cept cke are gated off to red u ce the powe r . the powe r do wn mode do es not perfo rm any refre s h ope ration s, therefo r e the device can n o t remain in powe r do wn mode lon g e r than the refresh p e rio d (t ref ) of the device. the po wer do wn mo de is exited by brin ging ck e high. when cke goe s high, a no ope r ation comm and is req u ire d o n the n e xt risi n g cl ock e dge, dep endi ng o n t ck . the in put buffers n eed to be enabl ed with cke held hig h for a peri o d equal to t cks (min ) + t ck (min). 7.18. no opera t ion comma nd the no o peration comma nd shoul d be use d in ca se s w hen th e sdram i s in a idle or a wait state t o preve n t the sdram fro m registe r in g an y unwante d comman d s b e t ween o perations. a no o peration comm and is regi stered wh en cs is low wi th ras , cas , and we held high at th e rising ed ge o f the clock. a no operation command wi ll not terminate a previous operation that is still executing, such as a bu rst rea d or write cycl e. 7.19. de sele c t command the de sele ct command perform s the same fun c tion as a no ope r atio n comma nd. desel e ct comm and o c cu rs whe n cs is broug ht hig h , the ras , cas , and we signal s be come do n?t cares. 7.20. clock sus p end mode du ring no rma l acce ss mod e , cke must be held high enabli ng the clo ck. wh en cke is regist ere d low while at lea s t one of the b anks i s a c tive, clo ck su spend m ode i s ente r ed. t h e clo c k susp end mo de dea ctivates t he internal cl ock an d su sp end s any cl o c ked o peratio n t hat wa s cu rre ntly being execute d . there is a o ne clo c k del a y between th e regi strati o n of cke low and the time at which the sdram ope ration su spend s. while in clo c k suspend mod e , the sdram ig nores a n y ne w comma nd s that are issued. th e clo ck su sp e nd mod e is e x ited by br in ging cke hig h . there i s a one clo c k cy cle del ay from wh en cke return s hi gh to whe n cl ock suspen d mode i s exited. pub lica tio n relea s e da te:aug . 13 ,2 007 - 11 - revi si on a0 7
W9812G2GB 8. operati o n mode fully synch r o nou s ope rati ons a r e pe rforme d to latc h the comma nds at the p o sitive edg es of clk. table 1 sho w s the truth tab l e for the ope ration comm a nds. table 1 truth table (note (1), (2)) command device st at e cken -1 cken dqm b s0, 1 a 10 a0-a9 ,a11 cs ras cas we bank a c t i v e i d l e h x x v v v l l h h bank precharge an y h x x v l x l l h l precharge all an y h x x x h x l l h l w r i t e a c t i v e ( 3 ) h x x v l v l h l l write w i th auto -p recharge active (3) h x x v h v l h l l r e a d a c t i v e ( 3 ) h x x v l v l h l h read w i th auto- p recharge active (3) h x x v h v l h l h mode register s e t idle h x x v v v l l l l no ? o perati o n a n y h x x x x x l h h h b u rs t s t op a c ti v e (4) h x x x x x l h h l dev i c e des e l e c t a n y h x x x x x h x x x auto refresh idle h h x x x x l l l h self refresh entr y idle h l x x x x l l l h self refresh exit idle (s.r.) l l h h x x x x x x x x h l x h x h x x x clock suspend m ode entr y acti v e h l x x x x x x x x pow e r do wn mo de entr y idle active ( 5 ) h h l l x x x x x x x x h l x h x h x x clock suspend mode exit acti v e l h x x x x x x x x pow e r do wn mo de exi t an y ( po w e r l l h h x x x x x x x x h l x h x h x x data w r ite/ outpu t enable ac t i v e h x l x x x x x x x data w r i t e/o u tp ut di s abl e a c ti v e h x h x x x x x x x notes : (1) v = valid x = don?t care l = lo w level h = high level (2) cken signal is input leve l w h e n commands are provided. cken-1 signa l is the input level one clock cy cle before the comm and is issued. (3) t hese are sta t e of bank designated b y bs0, bs 1 signals. (4) device state is full page burst operation. (5) po w e r do wn mode can not be entered in the b u rst c y cle. when this command asserts in the burst c y cle, device state is clock suspend mo de. pub lica tio n relea s e da te: aug . 13 ,2 007 - 12 - revi si on a0 7
W9812G2GB 9. electrical characte r ist i cs 9.1. absolute maxi mum ratings p a ra me t e r s y m bo l r a t i n g u n i t input/output voltage v in, v out -0.3 ~ v dd +0 . 3 v powe r suppl y voltage v dd , v dd q -0.3 ~ 4.6 v ope r ating te mperature (-6 / -75) t op r 0 ~ 70 c ope r ating te mperature (-6 i ) t op r - 4 0 ~ 8 5 c storage t e m perature t stg - 5 5 ~ 1 5 0 c solderi ng te mperature (1 0s) t so lder 2 6 0 c powe r di ssi p a tion p d 1 w short ci rcuit output cu rre n t i ou t 5 0 m a note : ex p o sure t o conditions bey ond those listed under absolute ma x i mum rating s ma y adversel y affect the life and reliability of the device. 9.2. recommended dc o p erating conditions (ta = 0 to 70 c for -6/ - 75, ta= - 40 to 85c for -6i ) par a met e r s y m b o l m i n . t y p . m a x . unit powe r suppl y voltage v dd 3 . 0 3 . 3 3 . 6 v powe r suppl y voltage (for i/o buff er) v ddq 3 . 0 3 . 3 3 . 6 v input high vo ltage v ih 2 . 0 - v dd +0. 3 v input low vol t age v il - 0 . 3 - 0 . 8 v note : v ih (ma x ) = v dd / v ddq +1.2v for pulse w i d t h < 5 ns v il (mi n ) = v ss / v ssq -1.2v for pulse w i d t h < 5 ns 9.3. capa citan c e (v dd = 3.3v, f = 1 mhz, ta 25 c) par a met e r s y m b o l m i n . m a x . unit input cap a cit ance (a0 to a11, bs0, bs1, cs , ras , cas , we , dqm, cke) c i - 3 . 8 p f input cap a cit ance (clk) c clk - 3 . 5 p f input/output cap a cita nce c io - 6 . 5 p f note : these p a r a meters are p e ri odically sampled and not 100 % te sted. pub lica tio n relea s e da te:aug . 13 ,2 007 - 13 - revi si on a0 7
W9812G2GB 9.4. dc charac teristi cs (vdd =3.3v 0. 3 v , ta = 0 to 70 c for-6 /-75, ta= -40 to 85 c for -6i) - 6 / - 6 i - 7 5 par a met e r s y m . m a x . m a x . u n i t n o t e s oper ating cur r e n t t ck = min., t rc = m i n . active precharge command c y cling w i thout burst ope ration 1 bank operation i dd1 1 3 0 1 1 0 3 standb y curr ent t ck = min, cs = v ih cke = v ih i dd2 4 5 3 5 3 v ih / l = v ih (mi n )/v il (max.) bank: inactive st ate cke = v il (pow er dow n mode) i dd2 p 2 2 3 standb y curr ent clk = v il , cs = v ih cke = v ih i dd2 s 1 5 1 5 v ih / l = v ih (mi n )/v il (max) bank: inactive st ate cke = v il (pow er dow n mode) i dd2ps 2 2 m a no ope r ating cu rrent t ck = min., cs = v ih (mi n ) cke = v ih i dd3 7 0 6 5 bank: active stat e (4 banks) cke = v il (pow er dow n mode) i dd3 p 1 5 1 5 burst ope r ating curren t t ck = min. read/ write com m and c y cling i dd4 2 0 0 180 3 , 4 auto refresh c u rrent t ck = min. auto refresh com m and c y cling i dd5 2 3 0 2 1 0 3 self refresh cur r ent self refresh mo de cke = 0.2v normal (-6/- 6i/-75 ) i dd6 2 2 par a met e r s y m b o l m i n . m a x . unit not e s input leakage c u rrent (0v v in v dd , all other pins not under test = 0v) i i( l) - 5 5 a output l eakage curren t (outp u t disable , 0v v out v ddq ) i o( l) - 5 5 a lvttl output h level voltage (i out = -2 ma ) v oh 2 . 4 - v lvttl output l level voltage (i out = 2 ma ) v ol - 0 . 4 v pub lica tio n relea s e da te: aug . 13 ,2 007 - 14 - revi si on a0 7
W9812G2GB 9.5. ac characteristi cs an d operatin g conditio n (vdd =3.3v 0. 3 v , ta = 0 to 70 c for - 6 /-75, ta= -40 to 85 c for - 6 i, notes: 5, 6, 7, 8, 9, 10) - 6 / - 6 i - 7 5 par a met e r s y m . m i n . m a x . m i n . m a x . u n i t n o t e s ref/active to ref/active com m and per i od t rc 60 6 5 active to prech a rge c o mman d perio d t ras 4 2 1 0 0 000 4 5 100 0 0 0 n s active to read/ w r ite comman d dela y ti m e t rcd 1 8 2 0 read/w r ite(a) t o rea d /w rite(b ) command period t ccd 1 1 t ck prechar ge to active comman d perio d t rp 1 8 2 0 active(a) to active(b) comm and period t rrd 1 2 1 5 n s cl* = 2 2 2 t ck write recover y t i me cl* = 3 t wr 2 2 cl* = 2 10 100 0 10 100 0 clk cy cle t i me cl* = 3 t ck 6 1 0 0 0 7 . 5 100 0 clk hi gh le vel width t ch 2 2 . 5 9 clk lo w lev el width t cl 2 2 . 5 9 cl* = 2 6 6 access t i me fr om clk cl* = 3 t ac 5 5 . 4 10 output data hold t i me t oh 3 3 1 0 output data hi gh imped ance t i me t hz 3 6 3 7 . 5 8 output data lo w impe da nce t i me t lz 0 0 1 0 po w e r do w n m ode entr y t i me t sb 0 6 0 7 . 5 t r ansition t i me of clk (rise an d f a ll) t t 0 . 1 1 0 . 1 1 7 data-in s e t-up t i me t ds 1 . 5 1 . 5 9 data-in h o ld t i me t dh 1 . 0 1 . 0 9 address set-u p t i me t as 1 . 5 1 . 5 9 address h o ld t i me t ah 1 . 0 1 . 0 9 cke set-up t i me t cks 1 . 5 1 . 5 9 cke hold t i me t ckh 1 . 0 1 . 0 9 command set- up t i me t cm s 1 . 5 1 . 5 9 command hold t i me t cm h 1 . 0 1 . 0 ns 9 refresh t i me t ref 6 4 6 4 m s mode re gister set c y cl e t i me t rsc 1 2 1 5 n s exit self refres h to act i ve command t xsr 7 2 7 5 n s *cl = cas laten cy pub lica tio n relea s e da te:aug . 13 ,2 007 - 15 - revi si on a0 7
W9812G2GB note s: 1. operation excee d s ?a bsolute maximu m rating s? m a y cau s e pe rmane nt dama ge to the device s . 2. all voltages are refe ren c ed to v ss 3. these parameters de pe nd on the cy cl e rate an d listed values a r e mea s ured a t a cycle rate with the minimum val ues of t ck and t rc . 4. these parameters de pe nd on the out put loadin g condition s. sp ecified valu es are obtai ned with output ope n. 5. power u p seque nce is fu rther d e scribe d in the ?fun ctional de scri p t ion? sectio n. 6. ac testing conditio n s p a ra me t e r c o n d iti o n s output refe rence level 1.4v output loa d see diag ram belo w input signal l e vels (v ih /v il ) 2 . 4 v / 0 . 4 v tran sition ti me (t t : tr/tf) of input signal 1/1 ns input refe ren c e level 1.4v 50 oh m s 1. 4 v ac t e s t l o a d z = 50 oh m s ou t p u t 30 pf 7. tran sition times a r e me a s u r ed b e twe e n v ih and v il . 8. t hz defines the time at which the o u tp uts achieve t he ope n ci rcu i t condition a nd is not referenced to output level. 9. assum ed i nput transition t i me (t t ) = 1ns. if tr & tf is lon ger than 1ns, transie nt time compensation sho u ld be con s id ered, i . e . , [(tr + tf)/2-1]ns shou ld b e added to the parameter ( the t t max i mum can?t be more than 10ns for low frequenc y applicatio n.) 10. if c l ock rising time (t t ) is longe r than 1 n s, (t t /2-0.5 )ns sho u ld be adde d to the paramete r . pub lica tio n relea s e da te: aug . 13 ,2 007 - 16 - revi si on a0 7
W9812G2GB 10. timing waveform s 10.1. command input timing clk a0-a11 bs0, 1 v ih v il t cmh t cms t ch t cl t t t t t cks t ckh t ckh t cks t cks t ckh cs ras cas we cke t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah t ck pub lica tio n relea s e da te:aug . 13 ,2 007 - 17 - revi si on a0 7
W9812G2GB 10.2. re ad timing read cas latency t ac t lz t ac t oh t hz t oh burst length read command clk cs ras cas we a0-a11 bs0, 1 dq valid data-out valid data-out pub lica tio n relea s e da te: aug . 13 ,2 007 - 18 - revi si on a0 7
W9812G2GB 10.3. control timing of in put/output data t cmh t cms t cmh t cms t ds t dh t ds t dh t ds t dh t ds t dh valid data-out valid data-out valid data-out valid data-in valid data-in valid data-in valid data-in t ckh t cks t ckh t cks t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t cmh t cms t cmh t cms t oh t ac t oh t ac t oh t hz t lz t ac t oh t ac t ckh t cks t ckh t cks t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out clk dqm dq0 -31 (word mask) (clock mask) clk cke dq0 -31 clk control timing of input data control timing of output data (output enable) (clock mask) dqm dq0 -31 cke clk dq0 -31 open pub lica tio n relea s e da te:aug . 13 ,2 007 - 19 - revi si on a0 7
W9812G2GB 10.4. mode regi ste r set cy cle a0 a1 a2 a3 a4 a5 a6 burst length addressing mode cas latency (test mode) a8 reserved a0 a7 a0 a9 a0 write mode a10 a0 a11 bs0 "0" "0" a0 a3 a0 addressing mode a0 0 a0 sequential a0 1 a0 interleave a0 a9 single write mode a0 0 a0 burst read and burst write a0 1 a0 burst read and single write a0 a0 a2 a1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 a0 burst length a0 sequential a0 interleave 1 a0 1 a0 2 a0 2 a0 4 a0 4 a0 8 a0 8 a0 reserved a0 reserved a0 full page a0 cas latency a0 reserved a0 reserved 2 a0 3 reserved a0 a6 a5 a4 a0 0 0 0 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 0 0 1 t rsc t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah clk cs ras cas we a0-a11 bs0,1 register set data next command a0 reserved "0" "0" bs1 "0" "0" pub lica tio n relea s e da te: aug . 13 ,2 007 - 20 - revi si on a0 7
W9812G2GB 11. operati n g timin g example 11.1. interlea ved bank rea d (burst le ngth = 4, cas laten c y = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t rc t rc t ras t rp t ras t rp t rp t ras t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read precharge precharge precharge raa rbb rac rbd rae raa caw rbb cbx rac cay rbd cbz rae aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 bank #0 idle bank #1 bank #2 bank #3 pub lica tio n relea s e da te:aug . 13 ,2 007 - 21 - revi si on a0 7
W9812G2GB 11.2. interlea ved bank rea d (burst le ngth = 4, cas laten c y = 3, auto-prech arg e ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t rc t ras t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read t rc raa rbb rac rbd rae dq aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 ap* ap* ap* raa caw rbb cbx rac cay rbd rae cbz pub lica tio n relea s e da te: aug . 13 ,2 007 - 22 - revi si on a0 7
W9812G2GB 11.3. interlea ved bank rea d (burst le ngth = 8, cas laten c y = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t rc t rc t ras t rp t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 cz0 clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active read precharge active read precharge active t ac t ac read precharge t ac bank #0 idle bank #1 bank #2 bank #3 pub lica tio n relea s e da te:aug . 13 ,2 007 - 23 - revi si on a0 7
W9812G2GB 11.4. interlea ved bank rea d (burst le ngth = 8, cas laten c y = 3, auto-prech arg e ) a0-a9, a11 bank #0 idle bank #1 bank #2 bank #3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 raa raa cax rbb rbb cby rac rac caz * ap is the internal precharge start timing active read active active read t cac t cac t cac clk dq cke dqm a10 we cas ras cs read ap* ap* bs1 bs0 t ras t rp pub lica tio n relea s e da te: aug . 13 ,2 007 - 24 - revi si on a0 7
W9812G2GB 11.5. interlea ved bank writ e (burst le ngth = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 write precharge active active write precharge active write clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 idle bank #0 bank #1 bank #2 bank #3 t ras pub lica tio n relea s e da te:aug . 13 ,2 007 - 25 - revi si on a0 7
W9812G2GB 11.6. interlea ved bank writ e (burst le ngth = 8, auto-prech a r ge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rab rac ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 caz * ap is the internal precharge start timing clk dq cke dqm a0-a9 a11 a10 bs0 we cas ras cs bs1 active write write active bank #0 idle bank #1 bank #2 bank #3 ap* active write ap* pub lica tio n relea s e da te: aug . 13 ,2 007 - 26 - revi si on a0 7
W9812G2GB 11.7. page mode read (burst length = 4, cas l a tency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ccd t ccd t ccd t ras t rp t ras t rp t rcd t rcd t rrd raa raa cai rbb rbb cbx cay cam cbz a0 a1 a2 a3 bx0 bx1 ay0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 * ap is the internal precharge start timing clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active read active read read read read precharge t ac t ac t ac t ac t ac bank #0 idle bank #1 bank #2 bank #3 ap* pub lica tio n relea s e da te:aug . 13 ,2 007 - 27 - revi si on a0 7
W9812G2GB 11.8. page mode read / wri t e (burst l e ngth = 8, cas la ten c y = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras t rp t rcd t wr raa raa cax cay ax0 ax1 ax2 ax3 ax4 ax5 ay1 ay0 ay2 ay4 ay3 qq q q q q dd d d d clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active read write precharge t ac bank #0 idle bank #1 bank #2 bank #3 pub lica tio n relea s e da te: aug . 13 ,2 007 - 28 - revi si on a0 7
W9812G2GB 11.9. auto-prech arge read (burst len g th = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t ras t rp t ras t rp t rcd t rcd t ac active read ap* active read raa rab raa caw rab cax aw0 aw1 aw2 aw3 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 t ac ap* bx0 bx1 bx2 bx3 pub lica tio n relea s e da te:aug . 13 ,2 007 - 29 - revi si on a0 7
W9812G2GB 11.10. auto-prech arge writ e (burst len g th = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t ras t rp t ras t rp raa t rcd t rcd rab rac raa caw rab cax rac aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 active active write ap* active write ap* * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 pub lica tio n relea s e da te: aug . 13 ,2 007 - 30 - revi si on a0 7
W9812G2GB 11.11. auto re fre s h c y cle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 all banks prechage auto refresh auto refresh (arbitrary cycle) t rc t rp t rc clk dq cke dqm a0-a9, a11 a10 we cas ras cs bs0,1 pub lica tio n relea s e da te:aug . 13 ,2 007 - 31 - revi si on a0 7
W9812G2GB 11.12. self ref r e s h c y cle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq ck e dqm a0- a 9, a1 1 a1 0 bs 0 , 1 we ca s ra s cs t ck s t sb t ck s t ck s al l bank s pr ech a r g e sel f r e f r es h ent r y a r bi t r a r y cy cl e t rp sel f r e f r es h cyc l e t xs r no ope r at i o n / comma nd i n hi b i t s e lf r e fre s h ex it pub lica tio n relea s e da te: aug . 13 ,2 007 - 32 - revi si on a0 7
W9812G2GB 11.13. burs t re ad and single write (burst length = 4, cas l a tency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cs ras cas we bs0 bs1 a10 a0-a9, a11 dqm cke dq t rcd rba rba cbv cbw cbx cby cbz av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 qq q q d d d q qqq t ac t ac read read single write active bank #0 idle bank #1 bank #2 bank #3 pub lica tio n relea s e da te:aug . 13 ,2 007 - 33 - revi si on a0 7
W9812G2GB 11.14. po w e r do w n mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ra a c a a raa cax ra a ra a ax 0 ax 1 ax 2 a x3 t sb t ck s t ck s t ck s t sb t ck s ac tive s t an db y power down mode p r echarge s t an db y p o wer d o w n mode ac t i v e no p prechar g e no p ac tive no te : t h e p o w e r d ow n mo de i s e n te r e d b y a s s e r t in g ck e " l ow " . all i n p u t / outpu t bu f f e rs (ex c e p t ck e bu f f e rs ) are t u r n ed of f in t h e p o w e r d o w n mo de . w h e n c k e go es hi gh , c o m m a n d in pu t m u s t b e n o o p e r a t i o n a t ne x t cl k r i s i n g e d ge. v i o l ati n g ref r e s h re qui r e ment s du ri ng p o we r - dow n may r e su l t i n a lo ss o f dat a . clk dq ck e dq m a0-a 9 a11 a10 bs we cas ras cs read pub lica tio n relea s e da te: aug . 13 ,2 007 - 34 - revi si on a0 7
W9812G2GB 11.15. auto-prech arge timin g (read c y cle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note: t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq pub lica tio n relea s e da te:aug . 13 ,2 007 - 35 - revi si on a0 7
W9812G2GB 11.16. auto-prech arge timin g (write c y cle) act 01 3 2 (1) cas latency = 2 (a) burst length = 1 dq 45 7 68 9 1 1 10 write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 act ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 (2) cas latency = 3 (a) burst length = 1 dq write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 twr twr twr twr twr twr twr twr 12 act represents the write with auto precharge command. represents the start of internal precharing. represents the bank active command. write ap act act when the /auto precharge command is asserted,the period from bank activate command to the start of intermal precgarging must be at least tras (min). note ) clk pub lica tio n relea s e da te: aug . 13 ,2 007 - 36 - revi si on a0 7
W9812G2GB 11.17. timing chart of read to write cy cle note: the output data must be masked by dqm to avoid i/o conflict 11 10 9 8 7 6 5 4 3 2 1 0 (1) cas latency=2 in the case of burst length = 4 read read write write dq dq ( b ) command dqm dqm d0 d1 d2 d3 d0 d1 d2 d3 ( a ) command (2) cas latency=3 read write read write d0 d1 d2 d3 ( a ) command dq dq dqm ( b ) command dqm d0 d1 d2 d3 11.18. timing chart of write to read cy cle read write 0 11 10 9 8 7 6 5 4 3 2 1 q0 read q1 q2 q3 read read write write q0 q1 q2 q3 write q0 q1 q2 q3 d0 d1 dq dq ( a ) command dq dq dqm ( b ) command dqm ( a ) command ( b ) command dqm dqm in the case of burst length=4 (1) cas latency=2 (2) cas latency=3 d0 d0 d1 q0 q1 q2 q3 d0 pub lica tio n relea s e da te:aug . 13 ,2 007 - 37 - revi si on a0 7
W9812G2GB 11.19. timing chart of bu rs t st op c y cle (burst stop command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq q0 q1 q2 q3 bst ( a ) cas latency =2 command ( b )cas latency = 3 (1) read cycle q4 (2) write cycle command read command q0 q1 q2 q3 q4 q0 q1 q2 q3 q4 dq dq write bst note: represents the burst stop command bst 11.20. timing chart of bu rs t st op c y cle (precharge command) 01 1 1 10 9 8 7 6 5 4 3 2 (1) read cycle (a) cas latency =2 command q0 q1 q2 q3 q4 prcg read (b) cas latency =3 command q0 q1 q2 q3 q4 prcg read dq dq (2) write cycle (a) cas latency =2 command q0 q1 q2 q3 q4 prcg write (b) cas latency =3 command q0 q1 q2 q3 q4 write dq dq dqm dqm prcg twr twr pub lica tio n relea s e da te: aug . 13 ,2 007 - 38 - revi si on a0 7
W9812G2GB 11.21. cke/ d qm input timin g (write c y cle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk pub lica tio n relea s e da te:aug . 13 ,2 007 - 39 - revi si on a0 7
W9812G2GB 11.22. cke/ d qm input timin g (read c y cle) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q2 clk cycle no. external internal cke dqm dq q5 q4 ( 3 ) q4 clk clk clk q3 pub lica tio n relea s e da te: aug . 13 ,2 007 - 40 - revi si on a0 7
W9812G2GB 12. package specification 12.1. tfbga 9 0 balls pitch = 0.8mm d d2 e e 2 e e pub lica tio n relea s e da te:aug . 13 ,2 007 - 41 - revi si on a0 7
W9812G2GB pub lica tio n relea s e da te: aug . 13 ,2 007 - 42 - revi si on a0 7 13. revision history ve rsio n d a t e pag e de scri pt io n a01 mar. 24, 200 6 all create ne w d a tash eet a02 jul. 05, 200 6 8 burst stop co mmand a03 sep. 08, 200 6 10 exit auto refres h to next comman d is specifie d by t rc a04 sep. 27, 200 6 15,16 modify cha r a c teri stics notes 9 an d add note s 10 (t t ) a05 apr. 12, 2007 15,32,34,4 1 add t xsr timing spe c ificatio n and pa ckag e dimen s io n ball openi ng a06 jun. 21, 20 07 3,13,14,15 add -6i grade a07 aug. 13, 200 7 16 revise tran si ent time t t ac test co nditi on and cal c ul ate formula fo r co mpen satio n consi d e r ation i n note s 6, 9 of ac ch ara c te ristics and o p eratin g co ndi tion important notice winbond pr oducts are not designed, intended, authori z ed or w a r r a n te d for use as components in s y stems or equip m ent inten d ed fo r su rg ical implanta tion, atomic energ y control instrumen t s, airplane or spaces hip instruments, transpo r tation instru ments, tra ffi c signa l instrumen t s, combustion control ins t ruments, or for other ap plications in tend ed to s u pport or sustain life. furth er more, winbond produc ts are not intende d for applications w h erei n failure of winbon d products c ould result or lead to a situation w h erein per s onal injur y , death or sev ere propert y or en v i r onmental damage could occur. winbond cu stomer s usi ng or selling these pro d u c ts fo r use in such application s do so at thei r o w n risk an d agree to fully indemnif y winbond for an y damages resul t ing from such imprope r use or sale s .

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